Semiconductor devices are typically constructed en masse on a silicon or gallium arsenide wafer through a process which comprises a number of deposition, masking, diffusion, etching, and implanting steps. When the devices are sawed into individual rectangular units, each takes the form of an integrated circuit (IC) die. In order to interface a die with other circuitry, it is (using contemporary conventional packaging technology) mounted on a lead frame paddle of a lead-frame strip which consists of a series of interconnected lead frames, typically ten in a row. The die-mounting paddle of a standard lead frame is larger than the die itself, and it is surrounded by multiple lead fingers of individual leads. The bonding pads of the die are then connected one by one in a wire-bonding operation to the lead frame's lead finger pads with extremely fine gold or aluminum wire. Following the application of a protective layer to the face of the die, it, and a portion of the lead frame to which it is attached, is encapsulated in a plastic material, as are all other die/lead-frame assemblies on the lead-frame strip. A trim-and-form operation then separates the resultant interconnected packages and bends the leads of each package into the proper configuration.
In the interest of higher performance equipment and lower cost, increased miniaturization of components and greater packaging density have long been the goals of the computer industry. IC package density is primarily limited by the area available for die mounting and the height of the package. Typical computer-chip heights in the art are about 0.110 inches. A method of increasing density is to stack die or chips vertically.
U.S. Pat. No. 5,012,323, issued Apr. 30, 1991, having a common assignee with the present application, discloses a pair of rectangular integrated-circuit dice mounted on opposite sides of the lead frame. An upper, smaller die is back-bonded to the upper surface of the lead fingers of the lead frame via a first adhesively coated, insulated film layer. The lower, slightly larger die is face-bonded to the lower surface of the lead extensions within the lower lead-frame die-bonding region via a second, adhesively coated, insulative, film layer. The wire-bonding pads on both upper die and lower die are interconnected with the ends of their associated lead extensions with gold or aluminum wires. The lower die needs to be slightly larger in order that the die pads are accessible from above so that gold wire connections can be made to the lead extensions (fingers).
U.S. Pat. No. 4,996,587 (referred to hereafter as '587) shows a semiconductor chip package which uses a chip carrier to support the chips within a cavity. The chip carrier as shown in the figures has a slot that permits connection by wires to bonding pads which, in turn, connect to the card connector by conductors. An encapsulation material is placed only on the top surface of the chip in order to provide heat dissipation from the bottom surface when carriers are stacked.
A Japanese Patent No. 56-62351(A) issued to Sano in 1981 discloses three methods of mounting two chips on a lead frame and attaching the pair of semiconductor chips (pellets) to a common lead frame consisting of:
method 1 two chips mounted on two paddles; PA0 method 2 one chip mounted over a paddle and one below not attached to the paddle; and PA0 method 3 one chip attached above and one chip attached below a common paddle. PA0 a lead-frame paddle supported by a lead frame; PA0 a controlled, first, thin-adhesive layer affixing a first die above the paddle; PA0 a plurality of thin wires having a first low-loop wire bond to a plurality of first die-bonding pads and a second wire bond to a plurality of adjacent lead-frame lead fingers; PA0 a second thin-adhesive layer affixing a second die above the first die; PA0 a second plurality of thin wires having low-loop wire bonds to a plurality of second die-bonding pads and second wire bonds to the plurality of lead fingers; PA0 additional dies affixed above the second die, by additional subsequent layers of adhesive and having additional thin wires bonded to addition bonding pads and lead fingers; and PA0 an encapsulated layer surrounding all dies, adhesive layers, and thin wires.
The chips are apparently wired in parallel as stated in the "PURPOSE" of Sano.
The chips of patent '587 are also apparently wired in parallel by contacts on the "S" chips which contact the connection means.
It is the purpose of this invention to provide multiple stacked dies assembled in a special vertical configuration such that as many as four encapsulated dies will have a height no greater than existing 0.110-inch high dies and also have a separate lead and lead finger for each die pad connection.